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US Browse · Folsom · Other - Engineering & Technology

Other - Engineering & Technology in Folsom

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Building Automation Controls Systems Engineer
Johnson Controls Inc
Folsom, California, United States of America
Full time
Base: $73,400.00-$102,000.00; bonus/equity: not sp...
**
Mid-level
Bachelor's degree in engineering
3 years relevant experience
Hvac and building control systems design
The role involves supporting the design, configuration, and operation of complete building automation and control systems to ensure performance meets project requirements
41 days ago
Senior Ai Soc Architect
Intel Retiree Medical Plan Trust
Folsom, California, United States
Full time
Base: $223,470.00-361,200.00 usd; bonus/equity: st...
Senior
10+ years soc architecture experience
Pcie expertise required
Lead cross-discipline teams
The role involves defining and leading the development of next-generation Intel AI SoC Architecture from early pathfinding through execution
42 days ago
Gpu Performance Engineer
Intel
Folsom, California, United States
Full time
Base: $141,910.00-269,100.00 usd; bonus/equity: st...
**
Mid-level
Proven knowledge of gpu architecture
Experience with modern 3d rendering techniques
Hands-on experience with rtl debugs
The candidate will focus on optimizing modern workloads to achieve best-in-class performance for Intel's new Graphics Processing Units
48 days ago
Gpu Logic Design Engineer
Intel
Folsom, California, United States
Full time
Base: $122,440.00-232,190.00 usd; bonus/equity: st...
Hybrid
Mid-level
Rtl design and systemverilog coding
Gpu or cpu architecture experience
7 years industry experience with bachelor's
You will play a critical role in shaping the future of graphics and compute technologies by defining GPU IP designs
48 days ago
Physical Design Engineer - Cpu Core
Intel
Folsom, California, United States
Full time
Base: $105,650.00-200,340.00 usd; bonus/equity: st...
Hybrid
Mid-level
2+ years vlsi circuit design experience
1+ years static timing analysis
Low power design methodologies
This role involves executing the complete physical design flow for custom CPU designs from RTL to manufacturing-ready GDS
51 days ago
Physical Design Engineer - Cpu Core
Intel Corporation
Folsom, California, United States
Full time
Base: $105,650.00-200,340.00 usd; bonus/equity: st...
Hybrid
Mid-level
2+ years vlsi circuit design experience
1+ years static timing analysis experience
1+ years low power design methodologies
This role involves executing the complete physical design flow for custom CPU designs from RTL to manufacturing-ready GDS
51 days ago
Senior Design Verification Engineer- Mixed Signal Ip
Intel
Folsom, California, US
Full time
Base: $164,470.00-311,890.00 usd; bonus/equity: no...
Hybrid
Senior
Design verification experience
System verilog and ovm/uvm proficiency
Mixed signal microarchitecture specifications
Intel is committed to relentless innovation and transforming technology
53 days ago
Soc Design Engineer
Intel
Folsom, California, US
Full time
Base: $164,470.00-311,890.00 usd; bonus/equity: no...
On-site
Mid-level
Verilog and system verilog experience
Power and area efficient rtl design
Experience in semiconductor industry
The role involves developing logic design and RTL coding for graphics IPs
53 days ago
Gpu Physical Design Engineer Lead
Intel
Folsom, California, USA
Full time
$190,610.00-269,100.00 usd; not specified; health,...
Hybrid
Mid-level
Asic designs for integrated/discrete graphics and ai socs
Soc level physical design and optimization flows
Leading edge process technology and eda tools
The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc
57 days ago
Cpu Core Logic Designer
Intel
Folsom, California, US
Full time
$122,440.00-232,190.00 usd; not specified; not spe...
Hybrid
Mid-level
Cpu core logic design
Rtl coding and simulation
System verilog/verilog/vhdl
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs
57 days ago
Senior Dft Timing Signoff Engineer (sta)
Intel Retiree Medical Plan Trust
Folsom, California, US
Full time
$164,470.00-269,100.00 usd py
**
Senior
Primetime-based dft-mode timing constraints
Tessent dft architecture and implementation
Streaming scan network (ssn) concepts
We are seeking a highly skilled and hands-on DFT/STA Engineer to join our full-chip timing organization supporting next-generation AI processors
57 days ago
Senior Dft Timing Signoff Engineer (sta)
Intel
Folsom, California, United States
Full time
$164,470.00-269,100.00 usd; not specified; not spe...
**
Senior
Dft timing signoff
Primetime-based timing constraints
Tessent dft architecture
We are seeking a highly skilled and hands-on DFT/STA Engineer to join our full-chip timing organization supporting next-generation AI processors
57 days ago
Senior Dft Timing Signoff Engineer (sta)
Intel Corporation
Folsom, California, US
Full time
Base: $164,470.00-269,100.00 usd; bonus/equity: st...
Hybrid
Senior
Primetime-based dft-mode timing constraints
Tessent dft architecture and implementation
Streaming scan network (ssn)
We are seeking a highly skilled and hands-on DFT/STA Engineer to join our full-chip timing organization supporting next-generation AI processors
57 days ago
Cpu Core Senior Physical Design Engineer
Intel
Folsom, California, US
Base: $164,470.00-232,190.00; bonus/equity: stock ...
Hybrid
Senior
Cpu physical design implementation
Rtl to gds flow
Synthesis, place and route
Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing
58 days ago
Cpu Core Physical Design Engineer
Intel
Folsom, California, US
Base: $105,650.00-200,340.00 usd; bonus/equity: no...
Hybrid
Mid-level
Physical design implementation
Cpu physical design flow
Static timing analysis
Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing
58 days ago
Cpu Core Pre-si Validation/verification Eng
Intel
Folsom, California, US
Base: $141,910.00-200,340.00 usd; bonus/equity: st...
On-site
+3y experience
Cpu internals validation
Cpu integration validation
Validation methodologies and test plans
Defines, develops, and performs functional validation for CPUs, focusing on validation of the CPU internals and CPU integration in system level features for Intel performance and power efficient cores
58 days ago
Cpu Core Pre-si Validation/verification Eng
Intel
Folsom, California, US
Base: $141,910.00-200,340.00 usd; bonus/equity: st...
On-site
+3y experience
Cpu internals validation
Cpu integration validation
Validation methodologies and test plans
Defines, develops, and performs functional validation for CPUs, focusing on validation of the CPU internals and CPU integration in system level features for Intel performance and power efficient cores
58 days ago
Sr Fpga Firmware Engineer
Sierra Nevada Corporation Inc
Folsom, CA, United States
Base: $143,487.14 - $197,294.82; bonus/equity: ann...
**
Mid-level
Fpga hdl development, simulation and analysis
Vhdl language
Digital circuit concepts
Firmware engineers at Sierra Nevada Corporation research, design, develop, test, certify, deploy and improve cutting edge products and services
58 days ago
Soc Design Engineer
Intel Corporation
Folsom, California, US
Base: $164,470.00-311,890.00; bonus/equity: stock ...
On-site
Mid-level
Rtl coding and simulation
Graphics ips design
Power, performance, area, and timing goals
Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs
58 days ago
Cpu Core Senior Physical Design Engineer
Intel Corporation
Folsom, California, US
Base: $164,470.00-232,190.00 usd; bonus/equity: no...
Hybrid
Senior
Physical design implementation
Cpu microarchitectures
Eda vendor collaboration
Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing
58 days ago
Soc Design Engineer
Intel Retiree Medical Plan Trust
Folsom, California, US
Base: $164,470.00-311,890.00 usd; bonus/equity: st...
On-site
Mid-level
Rtl coding and simulation
Graphics ip design
Power, performance, area, and timing goals
Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs
58 days ago
Cpu Core Pre-si Validation/verification Eng
Intel Retiree Medical Plan Trust
Folsom, California, US
Annual salary range for jobs which could be perfor...
On-site
+3y experience
Cpu internals validation
Cpu integration validation
Validation methodologies and test plans
Responsibilities include defining, developing, and performing functional validation for CPUs, focusing on validation of CPU internals and CPU integration in system level features
58 days ago
Cpu Core Physical Design Engineer
Intel Retiree Medical Plan Trust
Folsom, California, US
Base: $105,650.00-200,340.00 usd; bonus/equity: no...
Hybrid
Mid-level
Cpu physical design flow
Vlsi circuit design and synthesis
Static timing analysis
Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing
58 days ago
Cpu Core Senior Physical Design Engineer
Intel Retiree Medical Plan Trust
Folsom, California, US
Base: $164,470.00-232,190.00 usd; bonus/equity: st...
**
Senior
Cpu physical design
Rtl to gds implementation
Timing closure
Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing
58 days ago
Sr Fpga Firmware Engineer
Sierra Nevada Corporation
Folsom, CA, United States
$143,487.14 - $197,294.82 py
On-site
Mid-level
Fpga hdl development
Vhdl language utilization
Digital circuit concepts
Firmware engineers research, design, develop, test, certify, deploy and improve cutting edge products and services
59 days ago

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Other - Engineering & Technology in Folsom

Building Automation Controls Systems Engineer

Senior Ai Soc Architect

Gpu Performance Engineer

Gpu Logic Design Engineer

Physical Design Engineer - Cpu Core

Physical Design Engineer - Cpu Core

Senior Design Verification Engineer- Mixed Signal Ip

Soc Design Engineer

Gpu Physical Design Engineer Lead

Cpu Core Logic Designer

Senior Dft Timing Signoff Engineer (sta)

Senior Dft Timing Signoff Engineer (sta)

Senior Dft Timing Signoff Engineer (sta)

Cpu Core Senior Physical Design Engineer

Cpu Core Physical Design Engineer

Cpu Core Pre-si Validation/verification Eng

Cpu Core Pre-si Validation/verification Eng

Sr Fpga Firmware Engineer

Soc Design Engineer

Cpu Core Senior Physical Design Engineer

Soc Design Engineer

Cpu Core Pre-si Validation/verification Eng

Cpu Core Physical Design Engineer

Cpu Core Senior Physical Design Engineer

Sr Fpga Firmware Engineer