Staff Dft Design Engineer

Indclutch

Penang, Malaysia
Not specified (assumed to be on-site in penang, malaysia).
10+ years dft design experience
Fpga and soc architecture leadership
Scan insertion and atpg pattern generation
Indclutch is seeking a Staff DFT Design Engineer in Penang, Malaysia, who will lead the development of design-for-test (DFT) strategies for complex FPGA designs. The role requires extensive experience in DFT implementation, collaboration across engineering teams, and a strong background in electrical engineering

Job Summary

  • Lead the definition of end-to-end DFT architecture and strategy for complex FPGA designs and platforms.
  • Drive advanced DFT implementation including scan insertion, ATPG, memory BIST, and streaming scan networks to ensure sign-off quality.
  • Collaborate with post-silicon teams to resolve failure analysis issues and drive yield improvement initiatives using silicon learning.

Matching Summary

Match Score: 85

Indclutch is seeking a Staff DFT Design Engineer in Penang, Malaysia, who will lead the development of design-for-test (DFT) strategies for complex FPGA designs. The role requires extensive experience in DFT implementation, collaboration across engineering teams, and a strong background in electrical engineering.

Skills & Requirements

Must-have

  • 10+ years DFT design experience
  • FPGA and SOC architecture leadership
  • Scan insertion and ATPG pattern generation
  • IEEE 1149.1 JTAG and IEEE 1687 IJTAG standards
  • SpyGlassDFT tool proficiency
  • Timing closure and power optimization strategies
  • Post-silicon debug and yield improvement

Nice-to-have

  • AI or LLM integration in DFT flows
  • Hands-on ATE platform exposure
  • Python, Tcl, Perl scripting skills
  • Low-power DFT test management expertise
  • Global team influence experience
  • Functional safety diagnostic coverage knowledge

Key Requirements

  • Bachelor's or Master's degree in Electrical/Electronic Engineering
  • 10+ years of industry experience in DFT design
  • Strong Verilog and SystemVerilog proficiency
  • Proven track record driving AI/LLM in DFT implementations

Work Rights

Not specified

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