Cpu Core Physical Design Engineer

Intel

Folsom, California, United States
Base: $105,650.00-200,340.00 usd; bonus/equity: st...
Hybrid
Vlsi circuit design and synthesis experience
Static timing analysis proficiency
Low power design expertise
Intel is seeking a Cpu Core Physical Design Engineer to join their Full Chip Timing Design Automation team in Folsom, California. This role focuses on the physical design implementation of CPU designs, requiring expertise in VLSI, static timing analysis, and low power design

Job Summary

  • The Full Chip Timing Design Automation team enables seamless timing closure and optimization across the entire backend flow.
  • Responsibilities include performing physical design implementation of custom CPU designs from RTL to GDS ready for manufacturing.
  • Intel offers a competitive total compensation package including stock bonuses, health benefits, and retirement programs.

Matching Summary

Match Score: 85

Intel is seeking a Cpu Core Physical Design Engineer to join their Full Chip Timing Design Automation team in Folsom, California. This role focuses on the physical design implementation of CPU designs, requiring expertise in VLSI, static timing analysis, and low power design.

Salary

Base: $105,650.00-200,340.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, vacation

Skills & Requirements

Must-have

  • VLSI circuit design and synthesis experience
  • Static timing analysis proficiency
  • Low power design expertise
  • CPU physical design flow knowledge
  • Bachelor's or Master's in STEM degree

Nice-to-have

  • x86 CPU architecture familiarity
  • TCL Perl Python programming skills
  • Collaboration with EDA vendors
  • Power frequency area optimization focus

Key Requirements

  • 1+ years VLSI circuit design experience
  • 1+ years static timing analysis experience
  • 1+ years low power design experience
  • Bachelor's or Master's in Computer/Electrical Engineering
  • US work authorization required for California location

Work Rights

Not specified

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