Junior Layout Engineer

NXP

Catania, Italy
0-2 years analog layout experience
Cadence virtuoso oa pvs expertise
Mentor graphics calibre drc lvs
NXP is building a new team in Catania to create high-impact microcontrollers as part of their intelligent AI at the Edge initiative

Job Summary

  • NXP is building a new team in Catania to create high-impact microcontrollers as part of their intelligent AI at the Edge initiative.
  • The role involves delivering floorplan activities at the IP level and running physical verifications including DRC, LVS, and DFM.
  • Candidates must demonstrate a strong focus on design for quality to ensure long-term reliability and zero defects in products.

Matching Summary

NXP is building a new team in Catania to create high-impact microcontrollers as part of their intelligent AI at the Edge initiative.

Skills & Requirements

Must-have

  • 0-2 years Analog layout experience
  • Cadence Virtuoso OA PVS expertise
  • Mentor Graphics Calibre DRC LVS
  • Device physics and ESD protection knowledge
  • IP level floorplan delivery

Nice-to-have

  • Cross-functional global collaboration skills
  • Technical training and guideline writing
  • Design for quality and reliability focus
  • Advanced parasitic extraction experience

Key Requirements

  • 0-2 years leading Analog layout activities
  • MSEE or BSEE degree required
  • Experience with complex ICs and device physics

Work Rights

Not specified

Tailored Resume

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